1. Field of the Invention
The present invention relates to a method of processing a thin film and a method of manufacturing a thin film semiconductor device and particularly a thin film transistor.
2. Description of the Related Art
FIGS. 1A to 1C are cross-sectional views showing a thin film transistor of a thin film semiconductor device, used to explain manufacturing processes therefor. As shown in FIG. 1A, for example, a gate electrode 2 made of Mo, Ta or the like is deposited on a glass substrate 1 and an oxide film 3 is formed by anodic oxidation so as to cover the gate electrode 2. A ground insulating film 4 made of SiN for shielding impurities or the like from the substrate 1 is formed entirely thereon so as to have a thickness of about 50 nm. A gate insulating film 5 is formed entirely thereon by a process of forming a first SiO.sub.2 layer. A first semiconductor layer 6 made of an intrinsic or low impurity concentration amorphous silicon forming a channel forming layer of a thin-film transistor to be finally formed is formed on an entire surface of the gate insulating film 5. The first semiconductor layer 6 is subjected to a first heating process employing laser irradiation (annealing) using an excimer laser irradiation for crystallizing the same, thereby the first semiconductor layer 6 being crystallized. As a result, the first semiconductor layer 6 becomes a polycrystalline semiconductor layer. Then, an SiO.sub.2 insulating layer 7, which is to be a stopper of etching to be carried out later on, is formed entirely on the first semiconductor layer 6 by a process of forming a second SiO.sub.2 layer.
As shown in FIG. 1B, the SiO.sub.2 insulating layer 7 is subjected to a pattern etching employing photolithography in which wet etching employing a fluorine etchant is carried out. The SiO.sub.2 insulating layer 7 on a portion of the first semiconductor layer 6 that is finally to be the channel forming portion is left. The SiO.sub.2 insulating layer 7 on other portions are removed by etching. Then, a second semiconductor layer 8 formed of an amorphous silicon semiconductor layer heavily doped with n-type or p-type impurity is deposited entirely. The second semiconductor layer 8 is subjected to a second heating processing with laser irradiation employing the excimer laser, for example, thereby the second semiconductor layer 8 being crystallized to make this semiconductor layer polycrystalline. An impurity from the second semiconductor layer 8 is diffused to the first semiconductor layer 6 thereunder with the insulating layer 7 being employed as a mask, and the impurity is activated.
As shown in FIG. 1C, the second semiconductor layer 8 and the first semiconductor layer 6 disposed thereunder are subjected to a pattern etching employing photolithography with the second semiconductor layer 8 which is an upper layer of two semiconductor layers being removed by etching except source-region and drain-region forming portions thereof and with the first semiconductor layer 6 which is a lower layer thereof being removed by etching except a pattern over its source-region and drain-region forming portions and its channel forming portion therebetween.
The pattern etching for the second and first semiconductor layers 8, 6 can be carried out by pattern etching employing the same photolithography. Specifically, etching for separating the source and drain regions of the upper second semiconductor layer 8 is carried out on the insulating layer 7, so that the insulating layer 7 serves as an etching stopper, i.e., an etching mask for the first semiconductor layer 6. Therefore, as shown in FIG. 1C, when the lower first semiconductor layer 6 is etched, the etching is not carried out below the insulating layer 7. As a result, only the source and drain regions of the upper second semiconductor layer 8 are separated. Since the insulating layer 7 is not deposited under the upper second semiconductor layer 8 at outer peripheral portions other than this separated portion, i.e., a portion where the source and drain regions are opposed to each other, the pattern etching of the upper second semiconductor layer 8 and the pattern etching of the lower first semiconductor layer 6 are carried out simultaneously.
In this case, to prevent the etching for separating the source and drain regions of the upper second semiconductor layer 8 from affecting the lower first semiconductor layer 6, this etching for separating the source and drain regions must be reliably carried out on the insulating layer 7. Therefore, an edge portion of the etching for the above separation is located at a position displaced inward from an edge portion of the insulating layer 7 by a predetermined width Ws in consideration of a positioning error, i.e., displacement caused upon the photolithography of the pattern etching, i.e., upon the positioning of an exposure mask relative to a photoresist.
Then, at least the channel forming portion of the first semiconductor layer 6 is subjected to hydrogenation processing for improving characteristics thereof by hydrogen plasma irradiation. Therefore, heat treatment is carried out by laser irradiation, for example, for restoring a damage caused on a semiconductor layer surface by impact or the like of ions generated by plasma upon the hydrogenation processing. In the heat treatment, entire deposition of an SiN film, not shown, prevents hydrogen introduced into the semiconductor layer from being diffused again, and an effect of the hydrogenation is more increased by introducing hydrogen contained in the SiN film into the semiconductor layer.
As described above, source and drain regions 9s, 9dare formed of the first semiconductor layer 6 left after the etching and the second semiconductor layer 8 whose impurity is diffused toward the former.
Source and drain electrodes 10s, 10d are respectively deposited on the source and drain regions 9s, 9d so as to have ohmic contacts. In this case, if the SiN is entirely formed as described above, electrode contact windows are formed therethrough and the source and drain electrodes 10s, 10d are deposited on and brought in contact with the source and drain regions 9s, 9d through the electrode contact windows. Thus, the thin film transistor is manufactured.
Employment of the above method of manufacturing the thin film transistor of the thin film semiconductor device encounters various problems. Specifically, since the insulating layer 7 is deposited on the channel forming portion of the first semiconductor layer 6 according to the above method, the hydrogen introduction to the semiconductor layer 6 is carried out through the insulating layer 7. Moreover, since the semiconductor layer 8 forming the source and drain regions is formed on the insulating layer 7 with being extended inward by the predetermined width Ws, when the hydrogen is introduced into a portion of the semiconductor layer 6 located below the portion of the semiconductor layer 8 extended onto the insulating layer 7 by the predetermined width Ws, the hydrogen is introduced along the surface direction of the insulating layer 7 as schematically shown by arrows a in FIG. 1C. Accordingly, the hydrogenation processing takes a long period of time, which lowers workability.
The above method requires two processes of forming SiO.sub.2 films which are the gate insulating film 5 and the insulating layer 7, requires a pattern etching employing photolithography for forming the insulating layer 7 in a predetermined pattern, and requires first and second heating processes employing laser irradiation for the first and second semiconductor layers 6, 8. This requirement complicates the manufacturing process.
Moreover, when the SiO.sub.2 layer is etched for forming the insulating layer 7, the fluorine etchant is usually employed. In this etching process, if a glass substrate is employed as the substrate 1, this fluorine etchant also etches the substrates 1 by a thickness corresponding to that of the SiO.sub.2 insulating layer 7. Specifically, if the thickness of the insulating layer 7 is 2000.ANG., for example, the substrate 1 is inevitably etched by 2000.ANG., which leads to the disadvantage that impurities such as Na, K or the like contained in the substrate, deteriorates and fluctuates characteristics of the transistor. The etching of the substrate contaminates the etchant and decreases lifetime of the etchant.
Since the alignment of the gate electrode 2 and the insulating layer 7, i.e., the alignment of the gate electrode 2 and the channel forming portion of the semiconductor layer 6 is not carried out accurately, an area where the gate electrode 2 is opposed to the source and drain regions is increased beyond necessity, which increases a parasitic capacitance between the gate and the source and drain. As a result, this increase of the parasitic capacitance lowers a switching speed and lowers a frequency characteristic. Moreover, it leads to uneven characteristics of the thin film transistor finally obtained and an increased ratio of manufactured secondary products.
Moreover, with the above method, it is difficult to manufacture a transistor having an offset structure in which the gate electrode is actively located away from the source and drain regions.